1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming contacts connecting to transistors and a substrate of an SOI device.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS and PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits having a critical dimension of 40 nm and less in the device level, thereby achieving an improved degree of performance in terms of speed and/or functionality. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance while, however, increasing dynamic power consumption of the individual transistors. That is, due to the reduced switching time period, the transient currents upon switching a CMOS transistor element from logic low to logic high are significantly increased.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance, at the location of a fast switching transistor, and thus reduce voltage variations which may otherwise unduly affect the logic state represented by the transistor.
Another important aspect of providing capacitors in advanced semiconductor devices is the incorporation of memory devices including dynamic random access memory (DRAM) devices, which typically require a charge carrier storage element. For example, sophisticated CPUs and also many other advanced integrated circuits require extended memory functionality, wherein the charge carrier storage capability of the capacitors may have an influence on the overall performance of the corresponding DRAM portion. Consequently, the respective trenches for accommodating an appropriate capacitor dielectric and capacitor electrode materials may have to extend deeply into the semiconductor material to provide the desired high capacitance.
As a consequence, a relatively high information storage density may be achieved on the basis of vertical capacitors, thereby enabling the incorporation of extended memory areas in highly complex integrated circuits. For example, due to the continuous shrinkage of features sizes in modern integrated circuits, the number of circuit elements per area unit may allow incorporating increasing functionality into a single chip, thereby achieving increased performance at reduced manufacturing costs. For example, as discussed above, the incorporation of extended memory areas into logic circuits, such as CPUs and the like, may significantly enhance the overall performance due to reduced access times for exchanging data between the CPU core and the memory areas. Thus, typically, so-called cache memories are incorporated into modern CPU designs, wherein access time and the semiconductor area required for defining a memory cell and the peripheral circuitry may be important design aspects. That is, a short access time for writing and reading data bits from a respective memory cell may be preferable in view of a high operating speed to reduce the number of clock cycles of the CPU core required for data exchange with the memory area. Consequently, memory architectures are highly desirable, which may allow short access times, which is typically realized by forming static memory cells that are basically flip flop circuits comprising a plurality of transistor elements so as to store a data bit by setting the state of the flip flop circuit as long as a required minimum supply power is supplied to the memory cell. For example, in currently preferred static memory cell architectures, six transistors are typically used for realizing a single memory cell, that is, for storing one bit of information. Thus, short access time may be accomplished at the cost of a moderately complex architecture of the basic memory cell, thereby requiring highly scaled transistor elements to increase the overall information storage density in static memory areas. On the other hand, by providing a storage element, such as a deep trench capacitor as described above, a basic memory cell may be realized by using a capacitor in combination with a single select transistor, which may therefore result in a significantly increased bit density due to the three dimensional configuration of the storage capacitor, which therefore makes a vertical storage capacitor very attractive for memory areas of high storage density, when less critical constraints with respect to access time are acceptable. That is, due to the requirement of shifting a relatively high amount of charge into the capacitor and from the capacitor for reading or writing a bit of information, the corresponding access time may be significantly higher compared to static memory cells, in which the access times are substantially defined by the switching times of the transistors. Moreover, moderately high amounts of charge leaking into surrounding substrate may have to be replaced on a regular basis, which may result in a moderately complex control regime which may have to be coordinated with respect to memory operations, such as read and write operations. This may also contribute to an overall increased access time for dynamic memory areas. In modern CPU designs, therefore, a certain hierarchy of memory devices may be provided such that memory architectures responding to the fastest available access time may be positioned close to the CPU core and may be used for the most time-critical memory operations, while restricting the memory size so as to not unduly consume valuable chip area. On the other hand, less time-critical data may be stored in memory areas having a high information density, such as the above-described dynamic RAM areas including vertical storage capacitors.
Thus, reducing the feature sizes of the active circuit elements, i.e., the transistors, may provide enhanced performance in time-critical logic blocks due to a reduced switching speed of transistors, for instance, in CPU cores and the like, while also contributing to an enhanced storage density in memory areas, in which a very high number of transistors may have to be provided per area unit. Typically, in complex integrated circuits, CMOS technology on the basis of silicon is one of the most prominent approaches due to the superior characteristics in view of operating speed, power consumption and cost efficiency due to the superior availability of the basic semiconductor material in combination with well-established process technologies and experience in forming integrated circuits over many decades. In CMOS technology, the basic circuit component is a field effect transistor, which may be provided in the form of an N-channel transistor and a P-channel transistor, in which highly doped drain and source regions are separated by a weakly doped channel region, which may exhibit the same or an inverse conductivity type compared to the highly doped drain and source regions. The conductivity of the channel region is controlled by a voltage supplied to a gate electrode, which is separated from the channel region by a thin insulating layer, also referred to as gate dielectric or gate insulation layer. The distance between the drain and source regions along the current flow direction, also referred to as channel length, which may substantially correspond to the length of the gate electrode, represents an important characteristic of the field effect transistor architecture, since, in combination with the charge carrier mobility, the channel length may substantially determine the overall conductivity and thus the switching speed of the transistor. Consequently, the gate length may represent a dominant design criterion for enhancing the performance of individual field effect transistors and thus of the entire integrated circuit.
With the shrinkage of the overall dimensions of individual transistor elements, resulting in increased packing density and thus reduced distance between neighboring circuit elements, in particular in dense circuit areas such as static RAM areas, as previously discussed, the lateral dimensions of contact structures and metallization systems may also be reduced. Typically, the number of interconnections between the individual circuit elements may be higher than the number of circuit elements so that an increasing packing density may impose even more severe constraints on the design and architecture of contact structures and metal layers, which provide the “wiring” of the individual circuit elements. In particular, the manufacturing sequence for forming contacts in a dielectric material which is formed around the transistor elements in the device level may represent one of the most critical process steps in highly scaled semiconductor devices, wherein the corresponding complexity of the respective manufacturing sequence may even further be increased in silicon-on-insulator (SOI) devices. The SOI architecture may frequently be employed in complex circuits due to significant advantages with respect to transistor performance. In an SOI configuration, a substantially crystalline substrate material, for instance typically in the form of silicon, has formed thereon an insulating layer followed by the actual silicon-based semiconductor layer in and on which the transistor elements are formed. Thus, respective active regions of individual transistor elements or of a group of transistor elements may be dielectrically isolated by the buried insulating layer and shallow trench isolation, which may result in enhanced transistor performance due to a reduced parasitic capacitance of the PN junctions in combination with reduced latch up effects and enhanced radiation immunity of the devices. On the other hand, the dielectric isolation of the semiconductor layer from the substrate material may be associated with a plurality of issues that are to be addressed.
For example, the buried insulating layer may result in an accumulation of charge carriers in the semiconductor layer during various phases in the overall manufacturing flow, for instance during ion implantation processes, plasma assisted etch processes, in particular in the metallization level, and the like, which may require a conductive connection between the semiconductor layer and the substrate material. Furthermore, the reduced thermal conductivity of the buried insulating layer may require a thorough temperature sensing regime across the substrate, which may frequently be accomplished on the basis of diode structures, which are typically formed in the substrate material, thereby also requiring conductive connection contacting the substrate diodes. Hence, a respective contact structure for SOI devices may comprise, in addition to the complex configuration of contact elements connecting to the circuit elements formed in and above the semiconductor layer, also substrate contacts extending from a height level of the semiconductor layer through the buried insulating layer and into the substrate material. Hence, the overall patterning sequence for forming the contact elements of SOI devices may become increasingly complex with reducing features sizes, as will be described with reference to FIGS. 1a and 1b. 
FIG. 1a schematically illustrates a semiconductor device 100 comprising a substrate 101 and a buried insulating layer 102. For example, the substrate 101 may represent a substantially crystalline semiconductor material having a certain base doping for defining a certain conductivity type. The buried insulating layer 102 is typically provided in the form of a silicon dioxide having a thickness of several tenths of nanometers and more. A silicon layer 103 is formed on the buried insulating layer 102 and may comprise, in the manufacturing stage shown, a plurality of isolation structures 104, such as shallow trench isolations (STI), thereby defining an “active” region 105 in and above which the transistor structures, such as a transistor 150, are formed. On the other hand, as previously discussed, other circuit elements may be formed on the basis of the substrate material 101. For example, a circuit element 160 may represent a portion of a substrate diode to be formed in the material 101. The substrate diode 160 may comprise a highly doped region 164, possibly in combination with a metal silicide region 166. Furthermore, sidewall spacers 163 may be formed on side-walls of a trench defined by the isolation structure 104 and the buried insulating layer 102. The transistor element 150 comprises a gate electrode structure 151, typically comprised of polysilicon material, which is separated from a channel region 155 by a gate insulation layer 152. As previously discussed, a critical dimension of the transistor 150 may be represented by the length of the gate electrode 151, i.e., in FIG. 1a, the horizontal extension thereof. For instance, the gate length of advanced transistor elements may be approximately 40 nm and less. Furthermore, sidewall spacers 153 may be formed on sidewalls of the gate electrode 151. Additionally, in the active region 105, drain and source regions 154 may be positioned laterally adjacent to the channel region. If required, metal silicide regions 156 may be formed in the drain and source regions 154 and the gate electrode 151, thereby reducing the contact resistance and also providing increased overall conductivity of the gate electrode 151. Furthermore, the transistor 150 and the substrate diode 160 may be enclosed and passivated by an interlayer dielectric material 110, which comprises an etch stop layer 112, for instance provided in the form of silicon nitride, followed by a silicon dioxide material 111. The interlayer dielectric material 110 comprises a plurality of contact elements 113A, 113B and 113C. As illustrated, different height levels for the contact elements 113A, 113B, 113C may be defined by the configuration of the transistor 150 and the substrate diode 160. That is, a first level corresponds to the height level of the gate electrode 151, while a second level corresponds to the height level of the semiconductor layer 103. Finally, a third level corresponds to the height level of the substrate material 101.
The semiconductor device 100 may be formed on the basis of the following processes. The isolation trenches 104 may be formed on the basis of established patterning and deposition processes wherein, prior to, during or after the formation of the isolation structures 104, a corresponding opening for the substrate diode 160 may also be created. Next, the gate electrode 151 and the gate insulation layers 152 may be formed on the basis of advanced techniques including advanced lithography and etch processes. Next, the spacer structure 153 may be formed in a common process with the spacers 163 and respective implantation processes may be performed to define the drain and source regions 154 and the heavily doped region 164 in a common process sequence. Thereafter, the metal silicide regions 156, 166 may be formed, if required, followed by the deposition of the interlayer dielectric material 110. After any planarization techniques, a patterning process is typically performed on the basis of an appropriate resist mask, possibly in combination with a hard mask, to define the lateral position and size for the contact elements 113A, 113B and 113C. During the corresponding etch sequence, the oxide material 110 may be etched while the layer 112 may act as a stop material.
As is evident, due to the very different height levels, highly selective etch recipes in combination with superior process control may be required. Thereafter, the etch stop layer 112 may be opened on the basis of a different etch chemistry, wherein an appropriate selectivity with respect to the metal silicide regions 156, 166 may also be required so as to not unduly etch into the underlying silicon material. Thereafter, well-established deposition processes, for instance for forming appropriate barrier materials such as titanium, titanium nitride and the like, are performed, followed by the deposition of an appropriate contact material, such as tungsten. Next, any excess material may be removed, thereby providing the configuration as shown in FIG. 1a. Thus, the patterning and the subsequent filling of the contacts 113A, 113B and 113C extending to very different height levels may therefore require high etch selectivity in combination with precise process control.
FIG. 1b schematically illustrates the device 100 in a situation wherein closely spaced transistors 170 are provided, for instance, in device areas requiring a high density of transistor elements, such as static RAM areas, as previously explained. In this case, the situation is even more complex since the formation of the respective contacts 113B for the transistors 170 may require an etch process for etching through a substantial amount of material of the etch stop layer 112, while in the transistor 150, a significant amount of oxide material of the layer 111 may still have to be etched for the contacts 113B, while the situation for the substrate diode 160 may be similar to that shown in FIG. 1a. Consequently, a high amount of oxide material may have to be removed for the circuit elements 160 and 150, while only a very low thickness may have to be etched in the transistors 170, which the imbalance between oxide and nitride may further increase for further device scaling, since then the interlayer dielectric material 110 may be substantially comprised of the layer 112 above the transistors 170. Thus, process controllability may be significantly reduced since the removal of the significant portion of the material 112 for the transistors 170 may require extended etch time, which may result in a substantially non-predictable etch conditions in the devices 150 and 160.
Therefore, it has been proposed that for highly scaled semiconductor devices corresponding to the 45 nm technology node and beyond, a separate patterning sequence for the substrate contacts 113C is to be performed. Hence, additional lithography and patterning processes may be added to the conventional manufacturing flow, as described with reference to FIG. 1a, thereby increasing overall production cost and cycle time.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.